Device parameters of two identically designed devices in an integrated circuit may show a variation after fabrication. The variation is called device mismatch. For transistors, device mismatch may include variations of device parameters such as gate length and width, gate oxide thickness, threshold voltage, and doping levels. Device mismatch can have a significant impact on circuit performance such as speed, accuracy and power consumption. A recent statistical analysis of experimental data revealed that a 30% variation (3σ) of transistors' drive-current within a chip causes an equal variation in the circuit signal propagation delay. With the continuing scaling of semiconductor processes, the problems of circuit performance variations due to device mismatch are becoming more pronounced. Furthermore, these problems can be amplified by the low-power and low-voltage operation preferred in commercial electronic products.
It is thus important for circuit designers to be able to predict circuit performance variations due to device mismatch. A conventional way of estimating the statistical distribution of circuit performance (mismatch analysis) is the Monte Carlo analysis. In the Monte Carlo analysis, device mismatch is modeled as a set of randomly generated samples that represent the probability distributions of device parameters. The circuit is then repetitively simulated with the random device samples and the statistics of the resulting performance are collected. One major drawback of this approach is the large number of circuit simulations needed. This number can be over hundreds to thousands. Another conventional way of the mismatch analysis, the worst case analysis, also suffers from the same problem. The number of simulations required by the worst case analysis is largely dependent on the number of device parameters. A recent study reported the number of the required simulations can exceed eight hundred.
For practical applications, methods of mismatch analysis that do not require repeated circuit simulations are highly desirable.